The present invention relates to automatic test configuration generation techniques for facilitating the repair of programmable circuits, and more particularly, to techniques for constraining the generation of test routes on a programmable circuit according to rules designed to facilitate the isolation and repair of defects.
Integrated circuits sometimes fail to operate properly as a result of defects. For example, the die of an integrated circuit may become scratched. The integrated circuit may fail to operate properly as a result of the scratch. As another example, circuit failures may be caused by a short that develops in the integrated circuit.
A programmable integrated circuit, such as a programmable logic device (PLD), is thoroughly tested after manufacturing to screen for any defects. When a defect is detected on a programmable circuit, a failed row of programmable circuit elements can be replaced with an extra redundant row of programmable circuit elements.
Programmable logic devices such as Altera's Stratix family of PLDs include rows and columns of programmable logic elements. Each logic element includes a register and a look-up table (LUT). During the production test phase of a PLD, the registers in each logic element are configured as scan chain registers. The scan registers are coupled together in test routes. Each test route connects a control point register and to an observation point register.
The logic elements are tested by applying test vectors at the control points. The test vectors are shifted into the control point registers. Output values for each test route are shifted out of the observation point registers. The output values are compared to expected values to determine if any programmable connections in the test route between the control point and the observation point have defects.
If the output values indicate a failure, the row at the observation point is replaced with a redundant row. This only eliminates a failure if the defect causing the failure exists in the row at the observation point.
Many types of PLDs use vertical drivers that drive signals from one row of logic elements to the next. In Stratix PLDs, there is no way to drive a signal into the same row the signal originated from using a single vertical driver. In Stratix, a vertical driver drives a signal between at least two different rows. When a vertical driver is coupled in a test route, an error observed at an observation point in one row may be caused by a defect that exists in a different row. Current test systems do not have a fast and effective way of determining which of two or more rows contains a defect.
One technique for identifying a row that contains a defect is now discussed. Each LUT in the route between the control point and the observation point is configured as an XOR gate. Then, every possible combination of input signals to each of the XOR gates are tested to determine which input is the source of the defect. For example, if a configured XOR gate has two inputs, then four combinations of logic signals (1 and 0) are applied to the two inputs to determine which input is defective. This test procedure is very difficult and time consuming to apply during production testing, because it requires tracking failures across multiple LUTs by applying numerous test vectors.
It would therefore be desirable to provide a more efficient mechanism for isolating defects on programmable circuits during production testing. It would also be desirable to provide techniques for isolating a localized failure on a programmable circuit that has vertical drivers.